Discussion:X86

Simple quéstion : x86 ce prononce X 86 ou Fois 86? --Coelacanthe 31 juillet 2006 à 00:51 (CEST)

x86 se prononce "X 86". JeromeJerome 23 septembre 2006 à 22:10 (CEST)

Show Me A Hand to Improve The Main Article Together

The Chronology of x86 Processors

Generation		Introduction	Prominent CPU models	Address Space			Notable features
				Linear	Virtual	Physical
x86	1st	1978	Intel 8086, Intel 8088(1979)	16-bit	NA	20-bit	16-bit ISA, IBM PC (8088), IBM PC/XT (8088)
		1982	Intel 80186, Intel 80188 NEC V20/V30(1983)				8086-2 ISA, embedded (80186/80188)
	2nd		Intel 80286 and clones		30-bit	24-bit	protected mode, IBM PC XT 286, IBM PC AT
	3rd (IA-32)	1985	Intel 80386, AMD Am386 (1991)	32-bit	46-bit	32-bit	32-bit ISA, paging, IBM PS/2
	4th (pipelining, cache)	1989	Intel 80486 Cyrix Cx486S/DLC(1992) AMD Am486(1993)/Am5x86(1995)				pipelining, on-die x87 FPU (486DX), on-die cache
	5th (Superscalar)	1993	Intel Pentium, Pentium MMX(1996)				Superscalar, 64-bit databus, faster FPU, MMX (Pentium MMX), APIC, SMP
		1994	NexGen Nx586 AMD 5k86/K5 (1996)				Discrete microarchitecture (µ-op translation)
		1995	Cyrix Cx5x86 Cyrix 6x86/MX(1997)/MII(1998)				dynamic execution
	6th (PAE, µ-op translation)	1995	Intel Pentium Pro			36-bit (PAE)	µ-op translation, conditional move instructions, dynamic execution, speculative execution, 3-way x86 superscalar, superscalar FPU, PAE, on-chip L2 cache
		1997	Intel Pentium II, Pentium III (1999) Celeron(1998), Xeon(1998)				on-package (Pentium II) or on-die (Celeron) L2 Cache, SSE (Pentium III), SLOT 1, Socket 370 or SLOT 2 (Xeon)
		1997	AMD K6/K6-2(1998)/K6-III(1999)			32-bit	3DNow!, 3-level cache system (K6-III)
	Enhanced Platform	1999	AMD Athlon, Athlon XP/MP(2001) Duron(2000), Sempron(2004)			36-bit	MMX+, 3DNow!+, double-pumped bus, Slot A or Socket A
		2000	Transmeta Crusoe			32-bit	CMS powered x86 platform processor, VLIW-128 core, on-die memory controller, on-die PCI bridge logic
			Intel Pentium 4			36-bit	SSE2, HTT (Northwood), NetBurst, quad-pumped bus, Trace Cache, Socket 478
		2003	Intel Pentium M Intel Core (2006), Pentium Dual-Core (2007)				µ-op fusion, XD bit (Dothan), first Intel IA-32 processor deployed in Apple Macintosh computers (Intel Core "Yonah")
			Transmeta Efficeon				CMS 6.0.4, VLIW-256, NX bit, HT
IA-64	64-bit Transition 1999 ~ 2005	2001	Intel Itanium (2001 ~ 2017)	52-bit			64-bit EPIC architecture, 128-bit VLIW instruction bundle, on-die hardware IA-32 H/W enabling x86 OSes & x86 applications (early generations), software IA-32 EL enabling x86 applications (Itanium 2), Itanium register files are remapped to x86 registers
x64	64-bit Extended since 2001	x64 is the 64-bit extended architecture of x86, its Legacy Mode preserves the entire and unaltered x86 architecture. The native architecture of x64 processors, residing in the 64-bit Mode, lacks of access mode in segmentation, presenting 64-bit architectural-permit linear address space, currently, only 48-bit of which is implemented; an adapted IA-32 architecture residing in the Compatiblity Mode alongside with 64-bit Mode is provided to support most x86 applications
		2003	Athlon 64/FX/X2(2005), Opteron Sempron(2004)/X2(2008) Turion 64(2005)/X2(2006)	40-bit			AMD64 (except some Sempron processors presented as purely x86 processors), on-die memory controller, HyperTransport, on-die dual-core (X2), AMD-V (Athlon 64 Orleans), Socket 754/939/940 or AM2
		2004	Pentium 4 (Prescott) Celeron D, Pentium D (2005)	36-bit			EM64T (enabled on selected models of Pentium 4 and Celeron D), SSE3, 2nd gen. NetBurst pipelining, dual-core (on-die: Pentium D 8xx, on-chip: Pentium D 9xx), Intel VT(Pentium 4 6x2), socket LGA 775
		2006	Intel Core 2 Pentium Dual-Core (2007) Celeron Dual-Core (2008)				Intel 64 (<<== EM64T), SSSE3(65nm), wide dynamic execution, µ-op fusion, x86 macro-op fusion, on-chip quad-core(Core 2 Quad), Smart Shared L2 Cache, first Intel 64-bit processor deployed in Apple Macintosh computers as IA-32 processor with 64-bit additional computing resources (Intel Core 2 "Merom")
		2007	AMD Phenom/II(2008) Athlon II(2009), Turion II(2009)	48-bit			Monolithic quad-core(X4)/triple-core(X3), SSE4a, Rapid Virtualization Indexing (RVI), HyperTransport 3, AM2+ or AM3
		2008	Intel Core 2 (45nm)	36-bit			SSE4.1
			Intel Atom				netbook or low power smart device processor, P54C core reused
			Intel Core i7 Core i5 (2009), Core i3 (2010)				QuickPath, on-chip GMCH (Clarkdale), SSE4.2, Extended Page Tables (EPT), x64 macro-op fusion, first Intel 64-bit processor deployed in Apple Macintosh computers as pure 64-bit computing resources (Intel Xeon "Bloomfield" with Nehalem microarchitecture)
			VIA Nano				hardware-based encryption; adaptive power management
		2010	AMD FX	48-bit			octa-core, CMT(Clustered Multi-Thread), FMA, OpenCL, AM3+
		2011	AMD APU A and E Series (Llano)	40-bit			on-die GPGPU, PCI Express 2.0, Socket FM1
			AMD APU C, E and Z Series (Bobcat)	36-bit			low power smart device APU
			Intel Core i3, Core i5 and Core i7 (Sandy Bridge/Ivy Bridge)				Internal Ring connection, decoded µ-op cache, LGA 1155 socket.
		2012	AMD APU A Series (Bulldozer, Trinity and later)	48-bit			AVX, Bulldozer based APU, Socket FM2 or Socket FM2+
			Intel Xeon Phi (Knights Corner)	48-bit			coprocessor OS powered PCI-E Card Formed coprocessor for XEON based system, Many Core Chip, In-order P54C, very wide VPU (512-bit SSE), LRBni instructions (8× 64-bit)
		2013	AMD Jaguar (Athlon, Sempron)	48-bit			SoC, game console and low power smart device processor
			Intel Silvermont (Atom, Celeron, Pentium)	36-bit			SoC, low/ultra-low power smart device processor
			Intel Core i3, Core i5 and Core i7 (Haswell/Broadwell)	39-bit			AVX2, FMA3, TSX, BMI1, and BMI2 instructions, LGA 1150 socket
		2015	Intel Broadwell-U (Intel Core i3, Core i5, Core i7, Core M, Pentium, Celeron)				SoC, on-chip Broadwell-U PCH-LP (Multi-chip module)
		2015/2016	Intel Skylake/Kaby Lake/Cannonlake (Intel Core i3, Core i5, Core i7)	46-bit			AVX3
		2016	Intel Xeon Phi (Knights Landing)	48-bit			Bootable and standalone accelerator supplement to Xeon system, Airmont (Atom) core based
		2016	AMD Bristol Ridge (AMD (Pro) A6/A8/A10/A12)	48-bit			Integrated FCH on die, SoC, AM4 socket
		2017	AMD Ryzen Series/AMD Epyc Series				AMD's implementation of SMT, Socket with over too many pins in the form of Intel LGA (4094, Epyc), on-chip multiple dies, Epyc would replace Opteron brand for server market
Software Emulation ARM64		2017	Windows 10 on ARM64				Cooperation between Microsoft and Qualcomm bringing Windows 10 onto ARM64 platform with x86 applications supported by CHPE emulator starting from 1709 (16299.15)
Era		Release	CPU models	Physical Address Space			New features

The above table is not effortless, so if some readers are friendly to translate it into French, any suggestion left here is welcome, then that would be grateful to improve the main article. Million thanks in advance!

Here I should make some further explanations about Virutal Address (VA) and Linear Address (LA). Linear Address is a continuous addressing space which could be utilised by the programmers to retrieve data directly. For 16-bit processors, such as Intel 8086, 16-bit addressing space is its linear address, and extended with additional 16-bit segmentors to address 20-bit physical space (1 MiB). In the enhanced 16-bit processors, such as Intel 80286, besides 16-bit linear address, protection mechanism has been introduced, with which linear addresses could be remapped into even larger physical space, 24-bit for 80286. 14 bits within 16-bit segmentors are used as segment selectors, so 14 + 16 = 30-bit virtual space is provided. As to the 32-bit processors, such as Intel 80386DX, the linear space has been expanded from 16-bit to 32-bit, both protection mechanism and segmentation have also been improved. Within 32-bit physical addressing space, there exist 14 + 32 = 46-bit virtual addressing space. Just like its name, Virtual Address (from the viewpoint of the natural similarity among different species, it is like an address, which is used to address data in space), unlike linear address which could address a space continuously and directly, in order to address the space represented by VA, system software and auxiliary storage might also get involved. Modern architectures without segmentation treat linear address as virtual address.

Physical Address (PA), is another thing farther from architecture (which programmers could not get in touch directly), but much closer to the physical platform (implementation). With Intel 80386 processor, paging, a more flexible method, is introduced. Paging MMU is an external unit between ISA processor and physical memory controller(s), it could be programmed, but all the jobs are done automatically. Comparing with segmentation, paging simplifies the design of multitasking system. 32-bit linear address would be further processed by paging unit and re-mapped to 32-bit physical space or less, similar as the process from 46-bit VA to 32-bit linear/physical space, but in essence they are different. With Pentium Pro, PAE is introduced, which extends the 32-bit physical space to 36-bit or even more. Segmentation and Paging could be used together in complicated system. Paging could be disabled, but segmentation is rooted onto the core of x86 architecture since it was introduced with Intel 8086 processor. It is the comprising feature of x86 architecture, so it would never be disabled, but it could be ignored when only paging method is needed in modern paging-only operating systems. In those systems, all the working segments are set to point to the same location with same size, in this situation segmenting mechanism is transparent to the system programmers. 46-bit virtual address could be fully mapped onto 46-bit physical memory space without auxiliary storage involved, when PAE-46 is implemented, and both segmentation and paging cooperate with other each.

x86-64 (AMD64) architecture is academically accepted as a 64-bit variety of x86 architecture. This architecture is largely based on and extended from the x86 architecture (starting from the IA-32 protected mode), but it lacks of segmentation feature, making it considered as the 64-bit instruction set extension of x86 in x64 processors (both AMD64 and Intel 64). There also exist bunch of people considering it as the 64-bit version of x86 instruction set, because it also reserves the entire the x86 architecture in its legacy mode. But there still leaves a question that has the x86 architecture evolved into its 64-bit form? Just put it aside, standing on a neutral position. Comparing with x86 architecture, which is based on segmentation for addressing, x86-64 heavily depends on the paging mechanism to address physical memory, and that is the only way. It might be the distinct difference among design philosophies behind Intel and AMD. Smartly enough, x64 processors link them two together without breaking each other's nature. AMD64 architecture permits the linear address (virtual address) up to 64-bit (currently, 48-bit implemented) and physical address up to 52-bit. On the Intel counterpart, the Intel 64 architecture permits the physical address up to 46-bit (46-bit virtual address in x86 architecture fully expanded). But how the larger space above 256TB (48-bit) on linear address map to the 52-bit (46-bit) physical address, in late 2016, Intel released a whitepaper on the further implementation of 57-bit virtual addressing space, and that might be the final revision of this 64-bit extended architecture.

From Intel 8086/8088 through Pentium 4, there exists 7 generations of x86 processors, after that, the x64 processors succeed the x86 history. x86-64 is the 64-bit architectural extension of industry-standard x86 architecture, this 64-bit architecture currently also reserves the x86 as legacy, following which one could also treat them as x86 processors. The x86 architecture is a 32-bit architecture, evolved from 16-bit processors such as 8086/8088, 80186/80188 and 80286. This architecture has been supplemented by instruction set extensions, such as MMX, SSE, 3DNow! Today both x86 and x86-64 architectures co-exist with each other on x86-64 processors, programmes written for them two both benefit from latest instruct set extensions introduced with newly x86-64 processors, such as AVX, AES and so forth. Software designed for x86 architecture could work on both x86 and x86-64 processors; but the programmes written for x86-64 could only work on x86-64 processors. For this special characteristic, it also got a name, x64 processor, meaning that it is a processor designed for 64-bit extended system. Both x86-64 and x64 are often used interchangeably, but the latter emphasises the 64-bit nature caused by extending. x86 and x32 could not be used interchangeably, because the latter only refers to the 32-bit environment backward supported by x86-64 architecture, rather than the real x86 architecture found on x86 processors or the legacy mode of x86-64 processors. Some people refer to the 32-bit environments of both x86 and x86-64 processors as "x86-32"; 16-bit environment as "x86-16"; 64-bit environment of x86-64 processors as "x86-64", because they deny the fact that x86-64 is the widely accepted 64-bit variety of x86 architecture. Their naming convention seems making both x86 and x86-64 consistent under the idealised architecture, "x86". But it would lead chaos, such as what is the thing the term x32 refers to? The "x86-32" or the "x86-64" in their convention? They just underestimate or ignore the complexities and confuse x86 and x86-64 architectures them both.

The product of extending x86 with 64-bit computing is x64 rather than x86, or in other words, the x86 architecture does not happen to change since introduced with Intel 80386 processor, only extended with 64-bit extension. And this 64-bit extension is realised on Intel processors through a processor feature, EM64T, Extended Memory 64 Technology. Enable it, the processor has the chance to enter into the IA-32e mode and utilise the 64-bit computing resources. Disable it, the processor acts like a traditional x86 processor. This processor feature could be disabled on the firmware or hardwire disabled by Intel before delievering towards to the market, such as the Prescott based 32-bit Pentium 4 and Celeron processors. The Intel processor supports such feature and enabled initially called IA-32 processor with EM64T enabled, later, in 2006, it is called Intel 64 processor. Several early K8 based 32-bit Sempron processors have the similary situation as 32-bit Prescott based Pentium 4 and Celeron. Nowadays, the firmware does not provide option for the users to disable the EM64T feature.

Intel Itanium processor was first presumed to be the successor of Intel Pentium III, incorporating a Pentium III level x86 hardware engine onto the final Itanium processor. In the IA-32 system environment, all the x86 operating system and applications could work like a Pentium III processor. In the Itanium system environment, only the x86 applications could work with help of operating system providing backward support, such as WoW64 on Windows XP 64-bit Edition. The CPUID of the first generation of Itanium denotes its family number is 7, or 786, succeeding Pentium Pro/II/III (686). The corresponding value of Pentium 4 is 0xf, or 15. 0xf did not say that Pentium 4 was the 15th generation of Intel 80x86 processor, but it was the last and final generation of 80x86 processors, no more successors! After Itanium failed to overtake the market of x86, Intel got back to its 6th generation of 80x86 age, even until today, current Core i7 processors embrace the family number, 6, the sixth generation of 80x86 processors. That is the very reason I changed that so-called 7th gen to Enhanced Platform. Those processors succeeded the 6th ones, and were succeeded by x64 processors. An x64 processor is a 64-bit processor based on x86 ISA but extended with a 64-bit extended ISA, currently, x86-64. Intel just utilises this ISA to put their 64-bit computing power to the then 64-bit ready software resources, rather than giving in towards the ISA designing power of AMD. Even though the x86-64 was initially brought by AMD, but it is heavily based on the x86 architecture, most efforts from Intel, so the netural and fair term to refer this architecture is x86-64. And the proper term to refer to the system and processor is x64. x86-64 processor might not always be equavalent towards the x64 processor, especially when it eliminate the legacy support of x86 in the furture.

Physical Addressing Space and x86 Architecture limitation

There exists one confused or misused term, 3 GB barrier, well, allow me to be frank, in fact this thing does not exist at all, only fabricated by minors. x86 or IA-32 is a 32-bit architecture evolved from the architecture introduced with the 16-bit Intel 8086 processor. Like all other 32-bit architectures (ISA), the linear addressing capacity is limited up to 4GB space. In order to break this limitation but not the already mature architecture, Intel introduced an additional processor feature, Physical Address(ing) Extension (PAE), with the function of paging engine extended on the Pentium Pro processor to address up to 64GB (36-bit) physical address space, still retaining the 32-bit linear address. Mapping 32-bit linear space to 36-bit (or more) physical space is all done by the paging engine itself, but the set-ups and maintenances involves the codes from system software, firmware and operating system. And how to fully utilise the most potential physical memory and provide a more convenient interface towards applications programmers need even more efforts from system software programmers. So it is not an intuitive job, and often brings troubles to them both.

On computing platform, partial physical addressing space is used to address the resources (registers) of devices. Like stack (data structure), this space is reserved from top goes downwards. For 16-bit processor (8086), the room located from 1MB downwards up to 640KB is often reserved for devices, such as VGA card. For enhanced 16-bit processor (80286), besides that the room located from 16MB to 15MB is reserved. And to the 32-bit x86 (IA-32) and 64-bit x64 processor, besides those mentioned, physical room located from 4GB through 3.5GB needs reserved at minimum. The platform could also reserved even more space downwards to within 2GB or even more. The reserved physical addressing space, which could not be utilised to address the system memory, even if the configured memory spans partial or the entire of those overlapped adresses, is called memory gap. The missing memory space (eaten up by memory gap(s)) needs remapping to upper physical address space in order to avoid resource wasted.

Since long time ago, the system memory modules do not (and impossible) to connect to the processor cores directly, the bridge between processor core(s) and the physical memory modules is the MCH (Memory Controllor Hub), like the famous P965 chipset. Modern processors integrate the similar logic onto the processor die shared with cores. Remapping the memory gap(s) requires the processor(s) and MCH both be able to address the physical space more than 4GB. Intel 945 series and most previous MCH can only address physical space up to (or much less than) 4GB, so even though the processor supports PAE and enabled, the firmware could not implement such function(s). Of course, if the platform is designed for the pure 32-bit computing, the firmware and hardware connection might also make the memory gaps remapping impossible. In those situations, the most potential physical memory space is 4GB, the most utilisable physical memory space is 3.5GB, and least wasted physical memory space is 512MB, if 4GB physical memory has been equipped onto the system.

Since Windows XP Service Pack 2 released, Microsoft decided not to support physical address space above 4GB for security and compatibility issues, so even using the PAE kernel, the maximum memory which could be used is 3.25GB like mentioned above.

An x64 processor is a 64-bit extended processor, rooting itself on the platform of 32-bit x86 system. So under Legacy Mode, it would utilise the PAE feature to address the physical space above 4GB. Take a look at the table above, taking Intel Core i7 Haswell, for example, the maximum 512GB memory space could be utilised with PAE feature. When in the IA-32e mode, it would address this 512GB natively.

This table is almost done with my efforts. If you are kind enough to translate it into French and bring out to the main article, that would help readers from all over the world. So I thank you in advance. --- Aaron Janagewen (me is just myself, without bounded or reflexed to the regions of all of my IPs)